foundations of embedded systems 7
Transactions on the I2C bus are defined in terms of the SDA and SCL
lines and their values relative to each other, with the device initiating the
communication (the master) driving the SCL line with the I2C clock (at some
speed typically less than 400 kHz as mentioned above).
To initiate an I2C bus transaction, the master first drives an address on the
bus and the addressed slave responds by driving an acknowledge transaction
(ACK) on the bus. To drive the slave address, the master drives SDA low
during the half cycle when SCL is high. This is referred to as the start bit. The
master then begins to drive a sequence of bits on the SDA line, setting the bit
on SDA in the half cycle while SCL is low, driving SCL high at which point
the value on SDA is read by the slave, then driving SCL low again in order
to set the next bit on SDA.
A slave generates an ACK during this sequence by driving a 0 on the SDA
line during the half cycle when the SCL is low and generates a NAK during
this sequence by driving a 1 (i.e., doing nothing) on the SDA line. To indicate
the completion of a sequence of bits, the master drives SDA from low to high
while SCL is high. This is referred to as the stop bit. Throughout these steps,
the clock (SCL) is driven by the master. We will refer to the data transmitted
between the last address bit and the stop bit as the payload.
9.3.3 I2C addresses in transactions
Each slave on the bus is allocated a pre-defined 7-bit address, but the ad-
dresses transmitted in I2C transactions are 8-bit. The I2C bus master ap-
pends an additional bit to each 7-bit address: A 1 when the transaction is
a read transaction, and 0 when the transaction is a write transaction. The
master and slave use this additional bit to distinguish between whether the
transaction is a read transaction or a write transaction.
For example, the Freescale MMA8451Q accelerometer
9
is an I2C slave with
9
Freescale Semiconductor
2014.
a 7-bit slave address of 0x1C. The MMA8451Q has a pin, SA0 which you
can use to change the default slave address the MMA8451Q will respond to:
When the SA0 pin is tied to ground, the MMA8451Q responds to I2C slave
address 0x1C; when SA0 is tied to VDD, the MMA8451Q responds to slave
address 0x1D. Figure
9.6 shows the block diagram of the MMA8451Q with SA0
tied to VDD. During a read transaction, the 8-bit address transmitted by the
master is 0x3B and during a write transaction, the 8-bit address transmitted
by the master is 0x3A.
In addition to the slave address which is the first part of an I2C transaction,
the payload of an I2C transaction typically also contains an additional register
address. Unlike the slave address which distinguish between different devices
connected to an I2C bus, register addresses are addresses of internal registers
in the I2C slave device and represent pieces of internal functionality in the I2C