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Intended Learning Outcomes for This Topic
2
➌ Enumerate the differences between PALs, PLAs/CPLDs, and FPGAs
By the end of this topic, you should be able to:
➋ Enumerate differences between a programmable processor and programmable logic
➍ Describe the fundamental difference between programming languages and HDLs
➊ Identify several different methods to use circuits to achieve computation
➎ Conceptualize an embedded system design based on the iCE40 FPGA
48
buslock=0, buslocker=-1, EX touches mem = 0
WB: [TAS],0
MA: []
EX: [ANDI],1
ID: [0xe100],0
IF: [0x6013],0
node ID=0, PC=0x80042ba, ICLK=1668327, sleep?=0
buslock=1, buslocker=0, EX touches mem = 0
WB: []
MA: [ANDI],2
EX: []
ID: []
IF: [0xd109],0
node ID=0, PC=0x80042bc, ICLK=1668328, sleep?=0
buslock=1, buslocker=0, EX touches mem = 0
WB: []
MA: [ANDI],1
EX: []
ID: [0xd109],0
IF: [0x6413],0
node ID=0, PC=0x80042be, ICLK=1668329, sleep?=0
buslock=1, buslocker=0, EX touches mem = 1
WB: [ANDI],0
MA: []
EX: [MOVBSG],1
ID: [0x6413],0
IF: [0xd109],0
node ID=0, PC=0x80042c0, ICLK=1668330, sleep?=0
buslock=1, buslocker=0, EX touches mem = 0
WB: []
MA: [MOVBSG],0
EX: [MACL],1
ID: [0xd109],0
IF: [0x410b],0
…
Multiplexing Hardware in Time: Microprocessors
3
16 + 8
Architectural
registers
clk
clk
data
Main
memory
Cache
address
data
addr
addr
clk
clk
data
clk
Memory-mapped
peripherals
Timer / RTC
UART
A/D Converter
Battery Monitor
Failure Monitor
Network Interface
= Structures modeled at bit-level, enabling monitoring of signal transition activity and SEUs during simulation
Programmable
clock source
Program
Counter
clk
Interrupt
Controller
Register File write-back
Memory Access
Execute
Decode
Fetch
Memory
Management
Unit (MMU)
▶︎
See Sunflower showpipe command
48
Multiplexing Hardware in Time: Microprocessors
4
It’s all just a collection of gates
Logic gates are chained in space to construct adders, multipliers, whole ALUs, pipelines, and so on
a
b
a op b
The whole processor is reused in time, to execute multiple iterations of algorithms
IF
ID
MA
WB
EX
Image source: Wikipedia
48
Multiplexing Hardware in Space: Programmable Logic Devices
5
Microprocessors
Fixed hardware; achieve different functionality by loading different programs
Programmable Logic
▶︎ Programmable in this case means configurable
▶︎ Achieve different functionality by wiring up generic components
▶︎ Generic components may be a collection of ANDs and ORs, a collection of lookup tables (LUTs), etc.
Logic gates are connected in a fixed configuration to construct adders, multipliers, whole ALUs, and so on
a
b
a op b
IF
ID
MA
WB
EX
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PALs, PLAs (CPLDs), and FPGAs
6
Historical progression
▶︎ The earliest programmable logic devices were one-time mask-programmable, not reprogrammable
▶︎ One of the earliest reprogrammable logic array devices was the Altera EP300 (1984):
Source: Altera
48
PALs, PLAs (CPLDs), and FPGAs
8
PAL Architecture: Programmable AND array and fixed OR Array
▶︎ Any of the macrocell’s inputs or its complement can be routed to any AND gate in the AND array
▶︎ Design is broken up into macrocells. Each macrocell is a sum of products
PALs (and PLAs, which we will see next) are a good match for designs that are mostly combinational logic
All the product terms are summed in a single OR gate for each macrocell
Source: Altera
48
PALs, PLAs (CPLDs), and FPGAs
9
PLA/CPLD: Programmable AND array and programmable OR Array
▶︎ Design is again broken up into macrocells
(Xilinx CoolRunner-II)
Source: Xilinx
48
PALs vs PLAs/CPLDs
10
PAL Architecture
Programmable AND array, fixed OR array
Both PALs and PLAs/CPLDs: ➊ have few sequential logic elements; ➋ do not scale to large designs
PLA/CPLD Architecture
Programmable AND and OR arrays
Source: Xilinx
Source: Altera