27
Intended Learning Outcomes for Today
2
➌ Use Yosys to check whether certain signal values are possible in your design
By the end of this session, you will be able to:
➋ Use Yosys to simulate parts of a combinational circuit
➍ Use Yosys to visualize your design at the gate and Verilog block levels
➊ Use the Yosys, ArachnePNR, and NextPNR tools for synthesis and place/route
➎ Use the Yosys and ArachnePNR or NextPNR tools, along with icetime, icepack,
and iceprog for synthesis and place/route, timing analysis bitstream conversion,
and configuring the iCE40 MDP evaluation board
27
3
A Simple Example
27
Simple Example
1 of 2
: Module Verilog
4
27
Use Yosys to Apply an Input to Combinational Logic
5
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt;
eval -set inSignal 1'b0 -show outSignal" simple.v
27
Use Yosys to Evaluate a Truth Table for a Combinational Block
6
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt;
eval -table inSignal" simple.v
27
Use Yosys to Check Satisfiability for a Set of Conditions
7
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt;
sat -set outSignal 1'b0" simple.v
27
Simple Example
2 of 2
: Verilog Testbench
8
27
Running Testbench Using iverilog
9
$ iverilog -o simple simple.v simpleTestbench.v; ./simple
27
10
A Larger Example
27
Larger Example
1 of 2
11
27
Larger Example
2 of 2
12
27
Use Yosys to Apply an Input to Combinational Logic
13
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt; eval
-set dataIn 8'h33 -set worstCaseDeviationCode 1'b1 -show M1dataIn -show
M1encoderOut -show encoderOut" e4Encoder_8bitData_1bitControl.v
27
Use Yosys to Evaluate a Truth Table for a Combinational Block
14
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt; eval
-table worstCaseDeviationCode,dataIn" e4Encoder_8bitData_1bitControl.v
27
Use Yosys to Check Satisfiability for a Set of Conditions
15
$ yosys -p "hierarchy -check; proc; opt; fsm; opt; memory; opt;
sat -set encoderOut 8'b01111111" e4Encoder_8bitData_1bitControl.v
27
Use Yosys to Visualize Design at the Logic Gate Level
16
$ yosys -p 'hierarchy -check; proc; opt; fsm; opt; memory; opt; techmap; opt;
splitnets -ports; show -lib ./simlib.v -format pdf -prefix
e4Encoder_8bitData_1bitControl-cmos -colors 33 -width -stretch'
e4Encoder_8bitData_1bitControl.v
Next, view the generated file e4Encoder_8bitData_1bitControl-rtl.pdf using a PDF viewer
27
Use Yosys to Visualize Design at the RTL-Block Level
17
$ yosys -p 'hierarchy -check; proc; opt; fsm; opt; memory; opt; show
-format pdf -prefix e4Encoder_8bitData_1bitControl-rtl -colors 33 -width
-stretch' e4Encoder_8bitData_1bitControl.v
Next, view the generated file e4Encoder_8bitData_1bitControl-rtl.pdf using a PDF viewer
27
18
A Hardware Example
27
Context: The MDP Evaluation Board and iCE40 FPGA
19
27
Example on Hardware: Toggling an I/O Pin in blink.v
20
27
The PCF
21
PCF
▶︎ Physical constraints file
▶︎ Specifies which signals in top-level are connected to which pins in package
PCF file syntax
set_io <signal name> <package pin name>
27
PCF for blink.v Example
22
set_io led[0] D3
Example: Connect signal led[0] to pin D3 of the uwg30 package on the MDP board
27
Use ArachnePNR to Place and Route the Design
23
$ arachne-pnr -d 5k -P uwg30 -p blink.pcf blink.blif -o blink.asc
--asc blink.asc
$ yosys -p "synth_ice40 -blif blink.blif; write_json blink.json" blink.v
$ sudo iceprog -S blink.bin
$ icepack blink.asc blink.bin
$ icetime -p blink.pcf -P uwg30 -d up5k -t blink.asc
27
Use NextPNR to Place and Route the Design
24
$ yosys -p "synth_ice40 -blif blink.blif; write_json blink.json" blink.v
$ sudo iceprog -S blink.bin
$ nextpnr-ice40 --up5k --package uwg30 --json blink.json --pcf blink.pcf
--asc blink.asc
$ icepack blink.asc blink.bin
$ icetime -p blink.pcf -P uwg30 -d up5k -t blink.asc
27
How Many Gates Does it Take to Blink an LED?
25
Using a custom circuit implemented directly in FPGA logic (using the D-flip-flop hard IP)
$ yosys -p "synth_ice40 -blif blinkDataflow.blif;
write_json blinkDataflow.json" dffHardIP.v blinkDataflow.v
$ nextpnr-ice40 --up5k --package uwg30 --json blinkDataflow.json
--pcf blink.pcf --asc blinkDataflow.asc
Using a C program, which runs on a processor,
which is in turn implemented using FPGA logic
$ yosys -q ../../../yscripts/sail.ys
$ nextpnr-ice40 --up5k --package uwg30 --json $(DESIGN).json
--pcf pcf/sail.pcf --asc sail.asc
Backup
27
