1
Blinking an LED using the iCE40 FPGA
and the Open-Source FPGA Tools
Version:
git changeset: 170:373da60b63aa0705868d6a651c2d72842dcea0bc,
Fri Apr 10 14:52:08 2020 +0100
Good judgment comes from experience, and experience comes from
bad judgment.
—Fred Brooks.
This course uses the iCE40 UltraPlus FPGA, a low-power small-pincount
FPGA from Lattice semiconductor. Because it can easily be configured from
a microcontroller, requires minimal additional hardware to integrate into a
design, and because it has built-in hardware for low-power serial communi-
cation (two I2C interfaces and two SPI interfaces) the iCE40 device is a good
fit for low-power embedded systems such as those based on the RISC-V proces-
sor you will use in this course. And, unlike other FPGAs, there is a com-
pletely open-source set of tools for using the iCE40 FPGA. In this course, we
will implement a version of the RISC-V processor architecture on the iCE40
FPGA. In this first warmup exercise, you will use a small hardware design,
implemented in Verilog, to blink an LED connected to one of the pins of the
FPGA.
1.1 Intended Learning Outcomes
By the end of this chapter, you should be able to:
1. Use the Yosys, ArachnePNR, and NextPNR tools for synthesis and place/route.
2 phillip stanley-marbell
2. Use Yosys to simulate parts of a combinational circuit.
3. Use Yosys to check whether certain signal values are possible in your
design.
4. Use Yosys to visualize your design at the gate and Verilog block levels.
5. Use the Yosys and ArachnePNR or NextPNR tools, along with icetime,
icepack, and iceprog for synthesis and place/route, timing analysis bit-
stream conversion, and configuring the iCE40 MDP evaluation board.
1.1.1 Things to look out for
Concepts people sometimes get confused by in this chapter include:
1. The difference between the concept of synthesis (performed by Yosys) and
place-and-route (performed by ArachnePNR and NextPNR).
2. The difference between configuring an FPGA with a configuration bit-
stream (sometimes also referred to as “programming”) and configuring a
microcontroller with a program.
1.1.2 The muddiest point
As you go through the material in this chapter, think about the following two
questions and note your responses for yourself or using the annotation tools
of the online version of the chapter. You will have the opportunity to submit
your responses to these questions at the end of the chapter:
1. What is least clear to you in this chapter? (You can simply list the section
numbers or write a few words.)
2. What is most clear to you in this chapter? (You can simply list the section
numbers or write a few words.)
1.1.3 Learning outcomes pre-assessment
Complete the following quiz to evaluate your prior knowledge of the material
for this chapter.
1.2 The iCE40 MDP Evaluation Board
The iCE40 FPGA is a state-of-the-art miniature FPGA. The specific variant
that we will use is the iCE5UP5K which is only 2.15×2.55 mm is size. The
iCE5UP5K contains 5280 lookup tables (LUTs) which you can use to implement
arbitrary digital logic. You will learn more about the FPGA and how to
design for the FPGA in Chapter 2.
foundations of embedded systems 3
The hardware evaluation board you are using in this course is the iCE40
Mobile Development Platform (MDP). It contains four of the iCE5UP5Ks (U1,
U2, U3, and U4 on the board and in the schematics). The DIP switch SW5
determines which one of them you program at a given time. The default
setting of SW5 with both switch positions ON will program the U4 FPGA
which is at the bottom side of the MDP board (Figure
1.1).
Figure 1.1: The MDP
board, contains four
iCE5UP5K FPGAs. You
will use FPGA U4 for this
exercise and we recom-
mend you use it for the
remainder of the course.
1.3 A simple Verilog design
The example below is a simple Verilog design. You can find it in the file
verilog/hardware/blink/blink.v (from the top of the project repository).
Like all Verilog designs, it is organized into modules which represent blocks of
functionality. The module blink has only an output (led) and has no inputs.
The design contains a wire (clk), a 1-bit register of flip-flop (LEDstatus) and
a 4-bit register (count). All FPGAs contain some number of fixed hardware
resources, such as clock generators. The iCE5UP5K contains a high-frequency
clock generator module, named SB
_
HFOSC, that outputs a 48 MHz clock. The
iCE5UP5K also contains a low-frequency clock generator, named SB
_
LFOSC,
module that outputs a 10 kHz clock.
The construct beginning with SB
_
HFOSC OSCInst0 on line 12 creates an
instance of the SB
_
HFOSC module, named OSCInst0. In creating this instance,
we wire up the output of the OSCInst0 clock generator module instance to
our wire clk.
The block of Verilog statements from lines 21 through line 29 are what
is called a procedural block. The hardware that will eventually correspond to
the statements inside an always procedural block such as this, is updated
simultaneously and this update occurs on the condition in parenthesis fol-
lowing the @ symbol: the signals in this list are called the sensitivity list. In
our example, the hardware changes state on each positive edge (posedge) of
the clk signal. Every 2.5 million positive clock cycle edges, the 1-bit register
LEDstatus will therefore toggle in value.
Lastly, the last statement in the design, on line 34, connects the 1-bit regis-
ter LEDstatus to the output of the module.
1 ‘define kFofE
_
HFOSC
_
CLOCK
_
DIVIDER
_
FOR
_
1Hz 24000000
2
3 module blink(led);
4 output led;
5
6 wire clk;
7 reg LEDstatus = 1;
8 reg [31:0] count = 0;
9
10 /
*
11
*
Creates a 48MHz clock signal from
4 phillip stanley-marbell
12
*
internal oscillator of the iCE40
13
*
/
14 SB
_
HFOSC OSCInst0 (
15 .CLKHFPU(1’b1),
16 .CLKHFEN(1’b1),
17 .CLKHF(clk)
18 );
19
20 /
*
21
*
Blinks LED at approximately 1Hz. The constant kFofE
_
CLOCK
_
DIVIDER
_
FOR
_
1Hz
22
*
(defined above) is calibrated to yield a blink rate of about 1Hz.
23
*
/
24 always @(posedge clk) begin
25 if (count > ‘kFofE
_
HFOSC
_
CLOCK
_
DIVIDER
_
FOR
_
1Hz) begin
26 LEDstatus <= !LEDstatus;
27 count <= 0;
28 end
29 else begin
30 count <= count + 1;
31 end
32 end
33
34 /
*
35
*
Assign output led to value in LEDstatus register
36
*
/
37 assign led = LEDstatus;
38 endmodule
To make our blink.v Verilog design meaningful to map to any of the
FPGAs on the MDP platform, we need a way to specify how signals from
the modules in the design (such as the sole led signal of the module blink)
should be mapped to pins on the FPGA. We achieve this mapping using what
is called a physical constraints file. When loading our design into an FPGA, we
provide a PCF file to the corresponding FPGA tools. The pin-control file
specifies that the signal led should be mapped to the pin named D3 in the
specific FPGA package that the design is loaded into:
1 #
2 # Pin configuration file (PCF) for place and route
3 #
4 # Sets output led to pin D3 (connected to LED D14) of the
5 # version of the package on the MDP board.
6 #
7 # More details on pinouts here:
8 #
9 # http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus
10 #
11 set
_
io led D3
1.3.1 Example: Synthesis, Place, and Route for the iCE40 Ultra FPGA
The first step in loading your Verilog design onto the FPGA is to convert the
textual description into a a digital logic design. This process is called synthe-
foundations of embedded systems 5
sis. To synthesize the design, run, change directory to
verilog/hardware/blink/
and run:
$ yosys -p "synth
_
ice40 -blif blink.blif; write
_
json blink.json" blink.v
To run place and route using
nextpnr:
$ nextpnr-ice40 --up5k --package uwg30 --json blink.json --pcf blink.pcf --asc blink.asc
1.3.2 Example: Loading the bitstream to the iCE40 Ultra FPGA
To convert the output ‘blink.asc‘ ASCII file to iCE40 .bin file:
$ icepack blink.asc blink.bin
Figure 1.2: The jumper
settings, on the iCE40 MDP
board for programming the
U4 FPGA.
To program the configuration RAM on the iCE40 Ultra Plus: First, make
sure the jumpers on J19 are both horizontal (Figure
1.2), next, make sure you
have plugged the MDP board into your PC and switched it on using switch
SW2 (the LCD display should light up white), then:
$ sudo iceprog -S blink.bin
If successful, the green LED, D14, should be flashing very bright at about
1 Hz.
1.4 Exercise: Modify the blink design to use the low-frequency os-
cillator on the iCE5UP5K
Modify the blink design to use the low-frequency oscillator on the iCE5UP5K.
What changes do you have to make to
blink.v and why?
1.5 Example: Measuring the power used by the different subsystems
of the FPGA running the blink design
The iCE40 MDP contains test points to allow you to measure the power used
by the different power supply rails of the iCE5UP5K FPGA on the board.
These test points are in pairs and are located on either side of the current
flow path and are separated by 1 Ω resistors.
Use the Digilent oscilloscope to measure the voltage at each of the power
supply rails of the iCE5UP5K when your blink design is running. You will
later use this as the basis for measuring the power being dissipated by each
of the four FPGAs in the iCE40 MDP evaluation board.
1.6 Measuring power on the MDP
First, make use you know how to use the oscilloscope to measure voltages.
You will want to connect the ground pin of the oscilloscope to ground, and
6 phillip stanley-marbell
to connect the oscilloscope probe to the probe point at which you want to
measure voltage. Keep in mind that the voltage at any of the supply rails
will have some amount of noise / interference and variation over time, so
you will need to understand how to use the oscilloscope to obtain an average
measurement over time.
The labelings of the probe points on the MDP board given in the schematic
are not all correct. The correct probe points for each of the 1Ω shunt resistors
in the supply path of FPGA U4 are
R197 (VCC
_
iCE
_
D / core): TP44, TP70
R196 (VCCPLL
_
IN
_
D / PLL): TP45, TP52
R198 (VPP
_
2V5
_
D / OTP programming): TP46, TP62
R201 (VCCIO0
_
iCE
_
D / IO bank 0): TP47, TP60
R199 (SPIVCCIO1
_
iCE
_
D / SPI IO bank): TP48, TP67
R202 (VCCIO2
_
iCE
_
D / IO bank 2): TP49, TP61
Use the provided probes to attain a secure connection to the rails you want
to measure.
1.7 Blinking the LED using softwareblink.c and the Sail RISC-V
Processor
Change directory to verilog/hardware/processor/source/softwareblink/.
There is a C program there that will blink the LED just as the Verilog design
did. While in that directory, run:
$ make
$ make install
This will compile the C program, convert the program to the format needed
by the Verilog design and copy it to the location needed for subsequent syn-
thesis.
You will then need to change directory back to the
f-of-e-tools/verilog/hardware/processor/
directory and run make there to synthesize the design using the results from
this directory and to program it to the FPGA.
foundations of embedded systems 7
1.8 The Muddiest Point
Think about the following two questions and submit your responses through
this
link.
1. What was least clear to you in this chapter? (You can simply list the section
numbers or write a few words.)
2. What was most clear to you in this chapter? (You can simply list the
section numbers or write a few words.)
